FIG. 2 shows a prior art semiconductor device having an air bridge wiring structure. In FIG. 2, the reference numeral 1 designates a first wiring layer provided on a semiconductor substrate 4 and having a plurality of conductors. Bridge posts 2 are disposed on the widened portions 1a of the conductors of the first wiring layer 1. Bridge plate 3 is provided straddling a plurality of bridge post portions 2. The reference character W1 designates the marginal wiring interval between adjacent portions 1a of the conductors of wiring layer 1 which is required in view of process and design considerations. The reference character W2a designates the wiring interval between adjacent conductors in the first wiring layer.
In order to produce an air bridge wiring structure on a semiconductor substrate 4, the conductors of first wiring layer 1 are produced by a lift-off method or an etching method. Thereafter, bridge posts 2 are produced on the portions 1a of the conductors of wiring layer 1 by a gilding method or a lift-off method. Finally, bridge plate 3 is produced straddling a plurality of bridge posts 2 by a lift-off method or a gilding method, thereby producing an air bridge wiring structure.
The prior art semiconductor device having air bridge wirings has been designed such that bridge posts 2 of the air bridge structure are arranged in straight lines. The portion 1a of each of the first wiring layer conductors on which a bridge post 2 is to be produced needs to have a broader width relative to the width of the main conductors to allow for pattern shift and mask alignment margin during production of the bridge posts 2. Therefore, the interval W2a between main conductors is unavoidably lengthened. When the bridge posts 2 ae to be high, the resist for producing the bridge posts 2 must be thick. Therefore, the size of the bridge posts 2 is increased and interval W2a is further increased. Furthermore, when the number of main conductors is large, the tendency to increased interval width is accentuated, which is disadvantageous to reductions in chip size and cost.